1. Field of the Invention
The present invention relates to a central processing apparatus, a control method therefore, and an information processing system.
2. Description of the Related Art
A calculation capability of each central processing apparatus (i.e., central processing unit (CPU) chip) in, for example, an information processing system has been on the increase over the years in concert with the development of semiconductor production process technologies and other such developments.
In order to utilize the high calculation capabilities of central processing apparatuses effectively, the memory bandwidth (i.e., memory access speed) per central processing apparatus in memory access needs to be increased.
Conventionally, a single system controller is connected to a central processing apparatus so that the system controller carries out an interleaving to distribute access requests to a plurality of memory media. Therefore, the conventional technique cannot enable the central processing apparatus to recognize that the interleaving is taking place.
This accordingly necessitates thickening the bus (i.e., increasing the number of signal lines) between the central processing apparatus and system controller, and, associated with this, a thickened bus needs to be provided between the system controller and memory media in order to secure a sufficient memory bandwidth per central processing apparatus.
As a result, the number of signal lines connected to the system controller grows large. This is significant obstacle to obtain a higher system performance at a lower cost.